Mentor Graphics Introduces the Industry's First Concurrent Chip-to-Board Solution for FPGA and PCB Design
WILSONVILLE, Ore.—(BUSINESS WIRE)—July 19, 2004—
Mentor Graphics Corporation (Nasdaq:MENT), the market
leader in printed circuit board (PCB) design software, today announced
I/O Designer(TM), a new solution that facilitates concurrent
chip-to-board design of field-programmable gate arrays (FPGAs) and the
PCB. Part of Mentor's continued effort to support electronics
companies' need to capitalize on the latest advances in PCB and FPGA
technology, the unique solution allows bi-directional communication
and data management throughout the process of implementing complex
FPGAs on to the PCB. In product case studies, by managing the FPGA and
PCB design concurrently, I/O Designer allowed users to reduce the
total PCB route lengths by more than 15 percent, resulting in fewer
routing layers, significantly reducing design time, optimizing system
performance and lowering product manufacturing costs.
"As the only EDA tool provider in the industry with expertise in
both PCB and FPGA design, Mentor Graphics is the first to offer
solutions for integrating these once separate design processes. I/O
Designer allows PCB designers more control early in the design
process, ensuring maximum productivity for the entire systems design
team," said Henry Potts, vice president and general manager, Systems
Design Division, Mentor Graphics. "Integrating FPGA and PCB design
processes is no longer just an important way to improve efficiency -
it has become imperative to ensure system performance and lower
product costs."
Integrated Chip-to-Board Design
The I/O Designer solution provides for concurrent design of the
FPGA and PCB by bridging these unique design environments and
automating the various processes needed to implement today's high
pin-count, high-speed FPGAs on to complex PCBs. Starting with early
hardware description language (HDL) descriptions of the FPGA, I/O
Designer's automated schematic symbol generation function provides PCB
designers the schematic symbols used to represent FPGAs in the PCB
design. Then I/O Designer incrementally and bi-directionally manages
pin assignments on the FPGA by:
-- Graphically assigning signals to designated pins in a guided
FPGA library environment;
-- Constraining pin mapping pre-synthesis to achieve optimal FPGA
and PCB interconnect;
-- Communicating allowable FPGA pin-swaps to the PCB solution;
-- Synchronizing pin-out assignments between the FPGA and PCB
solutions for rapid timing closure and routing completion;
-- Communicating constraints between the PCB and FPGA solutions;
-- Allowing designers to optimize their I/O Design for PCB
layout.
"With I/O Designer, our team has eliminated hours of time
previously spent manually checking and double-checking the FPGA
pinlist," said Arie Doorduin, electronic design engineer, Research and
Development, Astron. "With I/O Designer there is a clear, consistent
relationship between the pin assignment of the schematic and the
synthesis tool. As a result, absolutely no checking is required."
Pricing and Availability
I/O Designer is available immediately with pricing starting at
US$10,000. Part of Mentor Graphics' continued focus to address the
most complex PCB design challenges with industry leading technology
and integrated solutions, I/O Designer integrates Board Station(R),
Expedition(TM) and PADS(R) with the Mentor Graphics FPGA Advantage(R)
integrated flow as well as design tools from major programmable logic
vendors. More information can be found at
http://www.mentor.com/expedition/io_designer.html.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$675 million and employs approximately 3,700 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: www.mentor.com.
Mentor Graphics, and Board Station, PADS and FPGA Advantage are
registered trademarks and Expedition and I/O Designer are trademarks
of Mentor Graphics Corporation. All other company or product names are
the registered trademarks or trademarks of their respective owners.
Contact:
Mentor Graphics
Debra Layton, 720-494-1043
debra_layton@mentor.com
or
Weber Shandwick
Emily Taylor, 503-552-3733
etaylor@webershandwick.com
